1. Field of the Invention
The present invention relates to a chip size stack package, a memory module having the chip size stack package and a method for fabricating the memory module, and more particularly, the present invention relates to a stack package in which at least two semiconductor chips are stacked to accomplish a size substantially corresponding to that of the conventional semiconductor chip, a memory module having mounted thereon the stack package, and a method for fabricating the memory module.
2. Description of the Related Art
Nowadays, the increase in a capacity of a memory chip is undergoing rapid progress. In this regard, while a 128M DRAM is currently produced in large quantities, a 256M DRAM will instead be mass-produced in the near future.
As a method for increasing a capacity of a memory chip, i.e., for rendering a high integration rate, a technique of inserting more cells into a preset area of a semiconductor device, is disclosed in the art. However, it takes a lengthy period of time to develop such technique, and the technique requires a high precision with respect to forming a line width, etc. To cope with these problems, recently, a stacking technique which enables a high integration rate to be realized in a simpler manner, has been vigorously developed.
The term, xe2x80x9cstackingxe2x80x9d which is used in the semiconductor industry, means a method of doubling a capacity of a memory chip by heaping up at least two semiconductor chips in a vertical direction. By the stacking technique, for instance, and a 128M DRAM device can be constituted by two 64M DRAM devices and a 256M DRAM device can be constituted by two 128M DRAM devices.
Referring to FIG. 1, there is shown a typical example of stack packages which are produced using the stacking technique. As shown in FIG. 1, inner leads of a lead frame 11 are attached, using an adhesive, to a semiconductor chip 10 on an upper surface of which bonding pads are located. The inner leads are connected to the bonding pads through metal wires 12. The entire structure is molded by an encapsulate 13 in a manner such that outer leads of the lead frame 11 are exposed at sides of the semiconductor chip 10.
On the package constructed as just mentioned above, there is stacked another package having the same construction. In other words, outer leads of the upward positioned package are coupled to a middle portion of the lead frame of the downward positioned package, whereby an electrical connection between two packages is effected.
However, the stack package according to the conventional art suffers from defects in that a thickness of the entire stack package is increased. Moreover, since a signal must be transmitted from the outer leads of the upper package through the lead frame of the lower package, a signal transmitting path is overly lengthened. Furthermore, due to the fact that the leads of the upper and lower packages are coupled to each other by means of soldering, an inferior connection may result from an improper soldering.
To solve these defects, another conventional stack package as shown in FIG. 2 is disclosed in the art. As shown in FIG. 2, upper and lower semiconductor chips 1a and 1b having surfaces on which bonding pads are formed, are arranged in a manner such that the surfaces thereof are opposed to each other at a predetermined interval. Upper and lower lead frames 2a and 2b are bonded to the respective surfaces of the upper and lower semiconductor chips 1a and 1b on which surfaces the bonding pads are formed, and inner leads of the upper and lower lead frames 2a and 2b are electrically connected to the bonding pads by metal wires 3a and 3b. On the other hand, an outer end of the upper lead frame 2a is bonded to a middle portion of the lower lead frame 2b. The resultant structure is molded by an encapsulate 4 in a manner such that only outer leads of the lower lead frame 2b are exposed.
Nevertheless, the conventional stack package as shown in FIG. 2 still encounters drawbacks as described below. First, while a signal transmitting path is shortened, due to the fact that two metal wires each of which conducts a signal transmitting function, too closely adjoin to each other, a likelihood of signal interference to occur is increased when the upper and lower semiconductor chips are simultaneously driven.
Also, while a connection technique using a laser is employed in order to electrically connect the respective lead frames with each other, this technique induces a drawback in that the laser connection has semi-permanency. Consequently, if a flaw is caused in one semiconductor chip, two semiconductor chips should be discarded together.
In addition, because the respective semiconductor chips are completely molded by the encapsulate, heat dissipation cannot be effectively executed while the upper and lower semiconductor chips are driven. That is to say, since a heat sink cannot be adequately installed, heat dissipation cannot be implemented in a sufficient manner.
Accordingly, the present invention has been made in an effort to solve the problems occurring in the related art, and a primary object of the present invention is to provide a chip size stack package which prevents signal interference from being generated and shortens a signal transmitting path.
Another object of the present invention is to provide a chip size stack package in which an electrical signal connection between stacked semiconductor chips is realized through a simple process without using costly laser equipment.
Another object of the present invention is to provide a chip size stack package in which respective semiconductor chips are coupled with each other in such a way as to be capable of being easily detached from each other, whereby it is possible to prevent the chip size stack package from being discarded as a whole when a flaw is induced in one semiconductor chip.
Still another object of the present invention is to provide a chip size stack package which enables a heat sink to be attached to a board, whereby a heat dissipation characteristic is improved.
Yet still another object of the present invention is to provide a memory module having the chip size stack package and a method for fabricating the memory module.
In order to achieve the above objects, a chip size stack package according to the present invention is constructed as described below.
Two semiconductor chips are arranged in a manner such that their surfaces on which bonding pads are formed, are opposed to each other at a predetermined interval. Insulating layers are applied to the surfaces of the semiconductor chips on which surfaces the bonding pads are formed, in a manner such that the bonding pads are exposed. Metal traces are respectively deposited on the insulating layers and connected to the bonding pads. Solder balls electrically connect the metal traces with each other. One ends of metal wires are bonded to a side of one of the metal traces. Both sides of the semiconductor chips and a space between them are molded by an encapsulate, in a manner such that the other ends of the metal wires are exposed.
A memory module having the chip size stack package as described above is constructed as stated below.
A first recess having a size capable of receiving one semiconductor chip is defined on a first surface of a board on which surface electrode pads are formed. An adhesive is applied to an inner wall of the board which inner wall defines the first recess. One semiconductor chip of the stack package constructed as mentioned above is received in the first recess and bonded to the inner wall of the board by the adhesive. The other ends of the metal wires are bonded to the electrode pads, respectively, and an encapsulate molds connection regions of the outside connection terminals, the first recess and a space between the upper and lower semiconductor chips.
A method for fabricating the memory module having the above-stated construction, is implemented as given below.
After an insulating layer is applied on a surface of a wafer which has a plurality of semiconductor chips, the insulating layer is etched, whereby bonding pads of individual semiconductor chip are exposed. Then, after a metal layer is deposited on the insulating layer, the metal layer is patterned, and thereby, a metal trace which is connected to the bonding pads, is formed. Thereupon, the wafer is cut along a scribe line, and thereby, the wafer is divided into respective semiconductor chips.
On the other hand, a first recess having a size capable of receiving one semiconductor chip is defined on a first surface of a board on which surface electrode pads are formed. After one semiconductor chip is received in the first recess and bonded to an inner wall of the board which inner wall defines the first recess, the electrode pads of the board and one of the metal traces are electrically connected with each other through metal wires, respectively. Several solder balls are mounted to the metal trace of the other semiconductor chip. The solder balls are also mounted to the metal trace of the one semiconductor chip which is bonded to the inner wall of the board which inner wall defines the first recess, whereby the two semiconductor chips are staked one upon the other. Finally, sides of the resultant structure, the first recess and a space between the two semiconductor chips are molded by an encapsulate, in a manner such that a surface of the upper semiconductor chip is exposed.
By the features of the present invention, since metal traces are used in place of lead frames, signal interference is minimized. Also, due to the fact that lead frames are not used, costly laser equipment for connecting lead frames is not needed. Moreover, because an encapsulate molds only sides of stacked semiconductor chips, by removing the encapsulate from the sides of the stacked semiconductor chips, the stacked semiconductor chips can be easily detached from each other. Furthermore, by the fact that a surface of the semiconductor chip is exposed from the encapsulate, a heat sink can be attached thereto. More particularly, as the two semiconductor chips having the same thermal expansion rate are arranged while being centered on the solder balls, mounting intensity of the solder balls is increased.